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The HB56A472E belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56A472E is a 4M × 72 dynamic RAM module, mounted 18 pieces of 16-Mbit DRAM (HM5116400) sealed in TSOP package and 2 piece of 16-bit BiCMOS line driver (74ABT16244) sealed in TSSOP package. An outline of the HB56A472E is 168-pin socket type package (dual lead out). Therefore, the HB56A472E makes high density mounting possible without surface mount technology. The HB56A472E provides common data inputs and outputs. Decoupling capacitors are mounted on the module board.

The Micron 16Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual memory array (the 4 Meg x 4 is a dual 2 Meg x 4, and the 2 Meg x 8 is a dual 1 Meg x 8) with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the two internal banks is organized with 2,048 rows and either 1,024 columns by 4 bits (4 Meg x 4) or 512 columns by 8 bits (2 Meg x 8).

Read and write accesses to the SDRAM are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC- TIVE command, which is then followed by a READ or WRITE command. The address bits registered coinci- dent with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.