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| * 10 ns pin-to-pin logic delays on all pins * fCNT to 111 MHz * 216 macrocells with 4800 usable gates * Up to 166 user I/O pins * 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals * Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell * Slew rate control on individual outputs * User programmable ground pin capability * Extended pattern security features for design protection * High-drive 24 mA outputs * 3.3 V or 5 V I/O capability * Advanced CMOS 5V FastFLASH technology * Supports parallel programming of more than one XC9500 concurrently * Available in 160-pin PQFP, 352-pin BGA, and 208-pin HQFP packages |
| The XC95216 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of twelve 36V18 Function Blocks, providing 4,800 usable gates with propagation delays of 10 ns. See Figure 2 for the architec-ture overview. |
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PDF下载文件大小：66744KB |
| 厂家 | XILINX [Xilinx, Inc] |
| 简要 描述 |
XC95216 In-System Programmable CPLD |
| A | B | C | D | E | F | G | H | I | J |
| K | L | M | N | O | P | Q | R | S | T |
| U | V | W | X | Y | Z | 0 | 1 | 2 | 3 |
| 4 | 5 | 6 | 7 | 8 | 9 |
| XC95144-10PQ100I |
| XC95144-10PQ160C |
| XC95144-10TQ100C |
| XC95144-15PQ160C |
| VI-27MEU |
| VI-27NCW |
| XC95144-15PQ160I |
| XC95144-15TQ100C |
