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| • High-performance - 5 ns pin-to-pin logic delays on all pins - fCNT to 125 MHz • Large density range - 36 to 288 macrocells with 800 to 6,400 usable gates • 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range • Enhanced pin-locking architecture • Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals - Extensive IEEE Std 1149.1 boundary-scan (JTAG) support - Programmable power reduction mode in each macrocell - Slew rate control on individual outputs - User programmable ground pin capability - Extended pattern security features for design protection - High-drive 24 mA outputs - 3.3V or 5V I/O capability - Advanced CMOS 5V Fast FLASH™ technology - Supports parallel programming of multiple XC9500 devices |
Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the Fast CONNECT™ switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and 18 outputs. The Fast CONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. |
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| 厂家 | XILINX [Xilinx, Inc] |
| 简要 描述 |
XC9500 In-System Programmable CPLD Family |
| A | B | C | D | E | F | G | H | I | J |
| K | L | M | N | O | P | Q | R | S | T |
| U | V | W | X | Y | Z | 0 | 1 | 2 | 3 |
| 4 | 5 | 6 | 7 | 8 | 9 |
| XC9509K |
| XC9509L |
| XC95103SL |
| XC95103SR |
| XC95108 |
| XC95108-10PC84C |
| XC95108-10PC84I |
| XC95108-10PQ100C |
