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This new series of digital transistors is designed to replace a single device  and  its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors;  a series  base resistor and a base-emitter resistor.The BRT eliminates these individual components by integrating them into a single device. The use of a BRT can reduce both system cost and board space. The device is housed in the SOT-23 package which is designed for low power surface mount applications.

The MAX3805 is designed to provide up to 30in (0.75m) reach on 6-mil differential FR-4 transmission line, or up to 24ft (8m) on RG-188A/U type coaxial cable, for PRBS data from 9.95Gbps to 10.7Gbps. The MAX3805 adaptive equalizer reduces intersymbol interference, resulting in 20ps residual jitter after equalization. An internal feedback network controls the equalizer to automatically match frequency-dependent skin effect and dielectric losses. The MAX3805 provides LVCMOS-compatible output-enable and signaldetect functions.

The MAX3805 has separate supply connections for the internal logic and I/O circuits. This allows the currentmode logic (CML) input and CML output to be connected to isolated supplies for independent DC-coupled interfaces to 1.8V, 2.5V, or 3.3V ICs. The MAX3805 comes in a very small 3mm x 3mm package and consumes only 135mW.

The M54/74HC590 is a high speed CMOS8-BIT BINARY COUNTER REGISTER (3-STATE) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption.

These devices each contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR and a count enable input CCKEN. For cascading, a ripple carry output RCO is provided.

Expansion is easily accomplished by tying RCO of the first stage to CCKEN of the second stage, etc.

Both the counter and register clocks are positiveedge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.