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The Taiwan Memory Technology Synchronous Burst RAM family employs high-speed, low power CMOS design using advanced triple-layer polysilicon,double-layer metal technology. Each memory cell consists of four transistors and two high valued resistors.

The T35L6432A SRAM integrates 65536 x 32 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable ( CE ), depth-expansion chip enables (CE2 and CE2), burst control inputs (ADSC , ADSP , and ADV ), write enables (BW1 , BW2字 , BW3 , BW4 , and BWE ), and global write (GW ).

Asynchronous inputs include the output enable (OE ), Snooze enable (ZZ) and burst mode control (MODE). The data outputs (Q), enabled by OE , are also asynchronous.

Addresses and chip enables are registered with either address status processor (ADSP ) or address status controller (ADSC ) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV ).

Address and write controls are registered on-chip to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BW1 controls DQ1-DQ8. BW2 controls DQ9-DQ16. BW3 controls DQ17-DQ 24. BW4 controls DQ25-DQ32. BW1 , BW2 , BW3 , and BW4 can be active only with BWE being LOW. GW being LOW causes all bytes to be written. WRITE pass-through capability allows written data available at the output for the immediately next READ cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.

The SN65ALS1176 differential bus transceiver is designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines and meets TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendations V.11 and X.27.

The SN65ALS1176 combines a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, that can be connected together externally to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications.

The SN65ALS1176 is characterized for operation from –25°C to 85°C.

The Microchip Technology Inc. MCP3221 is a succes- sive approximation A/D converter with 12-bit resolu- tion. Available in the SOT-23 package, this device provides one single-ended input with very low power consumption. Based on an advanced CMOS technol- ogy, the MCP3221 provides a low maximum conver- sion current and standby current of 250 µA and 1 µA, respectively. Low current consumption, combined with the small SOT-23 package, make this device ideal for battery-powered and remote data acquisition applications.

Communication to the MCP3221 is performed using a 2-wire, I 2C compatible interface. Standard (100 kHz) and Fast (400 kHz) I 2C modes are available with the device. An on-chip conversion clock enables indepen- dent timing for the I 2C and conversion clocks. The device is also addressable, allowing up to eight devices on a single 2-wire bus.